1. Field of the Invention
The present invention relates to a display controller with a display memory circuit, and more particularly to a display controller with a display memory circuit in which a multi-port memory is used.
2. Description of the Related Art
A conventional display memory circuit is widely used for a display controller or a display system to control a display apparatus to display an image. For instance, in case of a matrix type display apparatus such as a liquid crystal display apparatus, the circuit of a display controller is integrated and installed adjacent to a display panel of the display apparatus. The display controller drives H data lines arranged in parallel to a vertical direction of the display panel directly.
FIG. 1 is a block diagram showing a conventional display controller and a peripheral circuit of the display controller. The display controller 106 includes a display memory 161, a latch circuit 162, a data line driving circuit 163, a memory control circuit 164 and a timing control circuit 165. Here, a drawing unit 107 carries out a drawing process, and a gradation voltage generating circuit 108 generates gradation voltages V0 to V9. Also, a gate line driving circuit 109 selects and drives V gate lines arranged in parallel to the horizontal direction of the display panel in accordance with scanning of the display frame. A display section has the size of H pixels×V pixels×8 bits.
The display memory 161 is a 2-port memory with an external port and a read port only for a reading operation and is configured as a display memory circuit in the display controller. The display memory 161 is accessed by the drawing unit 107 through the external port. The display memory 161 receives and stored therein RGB display data of H pixels×V pixels×8 bits for one frame transferred from the drawing unit 107. Then, the display memory 161 sequentially select read word lines or horizontal lines in response to the scanning of the display frame and outputs the RGB display data in units of H pixels×8 bits from the read port to the latch circuit 162.
FIG. 2 is a circuit diagram showing the simplest example of the memory cell of this conventional multi-port memory shown in Japanese Laid Open Patent Application (JP-A-Heisei 8-161890). A memory cell of the multi-port memory is connected with a write bit line and a read bit line, and is selected by a write word line and a read word line. The memory cell is asynchronously accessed through the read port and a write port as the external port.
The latch circuit 162 latches the RGB display data of H pixels×8 bits, which have been read out from the read port of the display memory 161, in synchronism with a display clock, and then outputs the latched data to the data line driving circuit 63.
The gradation voltage generating circuit 8 generates 64 gradation voltages expressed by gradation voltages V0 to V9. The data line driving circuit 163 converts the RGB display data into analog signals by selecting one of 64 gradation voltages for one pixel based on the RGB display data of H pixels×8 bits outputted from the latch circuit 162. Then, the data line driving circuit 163 drives the H data lines in the display section in parallel. The V lines are sequentially driven by the gate line driving circuit 109.
The memory control circuit 164 inputs the memory control signal including an address signal from the drawing unit 107 to control the writing operation into the display memory 61 by the drawing unit 107. Also, the memory control circuit 164 inputs a synchronization signal and a display clock signal of the display frame from the timing control circuit 165 to control the reading operation from the display memory 161.
The timing control circuit 165 inputs the timing control signal from the drawing unit 107 and generates the synchronization signal and the display clock signal of the display frame to output the latch circuit 162, the memory control circuit 164 and the gate line driving circuit. 109. Thus, the timing control circuit 165 carries out a timing control of the scanning of the display frame.
This conventional display controller 106 stops the transfer of image data from an external unit, and drives the display section based on the RGB display data already stored in the display memory 161, when the display image is not dynamically changed like a still image. On contrary, when the display image is a video image, only the RGB display data of a changed portion of the display image is transferred. Thus, a reduction in power consumption is achieved.
Next, FIG. 3 is a block diagram showing another example of a conventional display system shown in Japanese Laid Open Patent Application (JP-P2000-250733A). The conventional display system includes a drawing memory 181, a display memory 182, a transfer control section 183, a timing control section 184, a display control circuit 185, and a CPU 186. Here, the functions of the display memory 182 and the display control circuit 185 correspond to the function of the display controller 106 shown in FIG. 1. The drawing memory 181 and the display memory 182 are used as a display memory circuit in the display system.
The drawing memory 181 is a work memory for the CPU 186 to store an image data. The display memory 182 stores an image data for the CPU 186 as a display data, like the display memory 161 shown in FIG. 1.
The transfer control section 183 starts the control of the transfer of the image data from the drawing memory 181 to the display memory 182 in response to a transfer start signal b and outputs a transfer end signal to the timing control section 184. The timing control section 184 outputs the transfer start signal b to the transfer control section 183 in response to a transfer start signal a from the CPU 186 and a non-display period start signal after the transfer start signal is made valid. Then, the timing control section 184 outputs a transfer execution signal to the CPU 16 until the transfer end signal is inputted.
The display control circuit 185 reads out the RGB display data from the display memory 182 in a constant period to transfer the data to the display section, and outputs the non-display period start signal to the timing control section 184. The CPU 186 carries out the drawing processing. After writing operation into the drawing memory 181, the CPU 186 outputs the transfer start signal a to the timing control section 184.
In this display system, the display control circuit 185 reads out the display data from the display memory 182 in a constant period, and carries out D/A conversion to the read out display data to transfer the data to the display section. The period that the display data for one frame is transferred to the display section is a display period. The non-display period is usually very shorter than the display period. When the CPU 186 changes the display data, the CPU 186 writes a new drawing data in the drawing memory 181. In this initial state, the CPU 186 and the display control circuit 185 can asynchronously access the drawing memory 181 and the display memory 182, respectively, because the transfer control section 183 is not operating. After the writing operation of the drawing data into the drawing memory 181, the CPU 186 outputs the transfer start signal a to the timing control section 184. After confirming invalidation of the transfer execution signal, the CPU 186 writes the next drawing data in the drawing memory 181 to update the stored data to the next drawing data.
Next, when the CPU 186 outputs the transfer start signal a to the timing control section 184, the timing control section 184 outputs the transfer execution signal to the CPU 186, and the transfer start signal b to the transfer control section 183 in response to the non-display period start signal. The transfer control section 183 transfers the drawing data from the drawing memory 181 to the display memory 182 in response to the transfer start signal b. This period is the non-display period in which the drawing memory 181 and the display memory 182 are not accessed by the CPU 186 and the display control circuit 185. As a result, it is possible to carry out the above transfer normally. When the transfer is completed, the transfer end signal is outputted from the transfer control section 183 to the timing control section, and the transfer execution signal is made invalid by the timing control section 184. In the next display period, the updated display data of the display memory 182 is read out by the display control circuit 185 and is outputted to the display section. Therefore, the display data on the updating operation is never displayed, and the updated display data in units of frames is displayed. Thus, the display screen never fall into disorder.
In this way, in recent years, in the display controller of a portable equipment, high precision display and a multi-function such as a video image reproduction are progressing based on user demand. It is possible to accomplish the high precision display by increasing the capacity of a display memory. Also, it is possible to accomplish the multi-function by adding a drawing circuit or a CPU and the drawing memory to the display controller and by transferring the data from the drawing memory to the display memory during the non-display period, like the display system shown with FIG. 3.
However, in this case, the display memory needs a memory capacity to store the RGB display data for at least one frame in order to reduce consumption power during the data transfer. Also, the drawing memory also needs a memory capacity to store the drawing data for one frame. Therefore, the memory capacity of the display memory circuit becomes large, resulting in increase of the circuit scale of the display controller.
Also, a data transfer quantity from the drawing memory to the display memory increases and the consumption power increases. Especially, since the data are transferred in units of frames between the display controller and the drawing apparatus, the data transfer quantity increases, resulting in increase of the consumption power. As a result, the battery duration of the portable equipment becomes short.
Also, in the display system shown in FIG. 3 and containing the drawing memory and the display memory, the similar problems such as the increase of the circuit scale and the increase of consumption power are caused.